This disclosure assumes some familiarity with IEEE1149.1 and the standard JTAG specification which is taught elsewhere and will not be repeated here. As electronic circuit cards and assemblies of circuit cards become more complex, with increasing density and the continued trends toward miniaturization, physical access to internal nets on these circuit cards becomes more difficult each passing year. Traditionally, physically probing internal nets with an oscilloscope probe, logic analyzer probe, or a guided probe has been an effective method to provide diagnostic fault isolation of failed circuit cards, or to support debugging code during test development or to probe a properly functioning circuit card. With the advent of FPGA devices commonly having 500+ pins with a 0.02 inch spacing, and 32 or 64-bit data bus architecture as common place, or even worse, ball grid arrays (BGA) without any physical access, physically probing circuit cards and assemblies has become problematic. Probing a circuit card generally relates to acquiring logic states and logic state transition timings on internal nets that are difficult or impossible to physically probe, especially while the circuit card is performing responsive to dynamic functional stimulation.
The present disclosure is directed toward one or more of the problems set forth above.